India's First CPUs Are Ready for App Development
The Indian Institute of Technology (IIT) Madras has released the software development kit (SDK) for its open-source Shakti processor. Shakti depends on the open-source RISC-V guidance set engineering and was financed by the Indian Ministry of Electronics and Information Technology. The foundation promised that a development board will also be released soon.
The RISE group at IIT Madras started working on the Shakti project in 2016 with a plan to release a family of six classes of processors, each serving a different market. The group promised that the reference processors will be competitive with commercial offerings as in terms of area, performance, and power consumption.
Now India, like China and the European Union, are showing interest in designing their own processors, as opposed to depending on ones structured by U.S. producers.
With the release of the Shakti SDK, developers can start to develop applications for the Shakti processors, even before they're commercialized.
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E Class
The E Class is a 3-stage in-order processor targeted at installed gadgets, for example, Internet of Things (IoT) gadgets, robotic platforms, motor controls, and so on.
C Class
This is a 32-Bit 5 stage in-order microcontroller-class of processors supporting 0.2-1 GHz clock speeds. It's aimed at mid-range application workloads and has a low power profile, also, to help for optimal memory protection.
I Class
The I class 64-bit out-of-order processors support 1.5-2.5 GHz clock speeds and support for multi-threading. It targets mobile, storage, and networking applications.
M Class
The M stands for multi-core here, as the M class processors support up to eight CPU cores, which can also be I and C class cores.
S Class
The S class of Shakti processors is focused on workstation and server-type workloads tasks at hand. It's an improved form of the I class processor that features multi-threading support.
H Class
These are processors for the high-figuring-performance and analytics workloads tasks at hand. Their primary features a high single-tread performance, optimal L4 cache, just as helpful for Gen-Z fabric and storage-class memory.
Experimental Designs
The RISE group is also working on two new experimental classes of processors. The first is the T class, which should bolster object-level security and coarse grain tags for macro-VM-like functionality to migrate software attacks like the buffer overflow.
The second is the F class, which can be thought of as an update over the T class with extra help for excess register squares and transport textures, ECC memory, and functionality to detect permanent faults.
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